This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Most receiver interfaces are implemented with a delay element that nominally applies a phase shift of 90 degrees to an input clock signal (A) to produce a phase-shifted output clock signal (Z) that can be used, for example, to sample a received data signal. Since the amount of delay provided by a delay element can drift over time due to variations in voltage (V) and/or temperature (T), a receiver interface is typically implemented with a configurable delay element that can delay the input clock signal Z by an amount of delay selected from a range of possible delay values. Such a receiver interface will also include a delay-locked loop (DLL)-based controller that dynamically generates and updates the delay code (i.e., control signal) used to select and change the amount of delay provided by the configurable delay element to track V/T variations during operation.
FIG. 1 shows a schematic block diagram of a prior-art configurable delay element 100 that can be used to provide a selectable phase shift in a receiver interface. Delay element 100 applies a selected amount of delay to an input (e.g., clock) signal A to generate a delayed (i.e., phase-shifted) output (e.g., clock) signal Z, where the amount of delay is selected from 128 different possible amounts of delay based on a 7-bit delay code SEL<6:0>.
In particular, delay element 100 has a delay chain 110 consisting of 128 serially connected, non-inverting buffers, where AND gate 112 functions as the first buffer and is followed by 127 inverter-based buffers 114, where each inverter-based buffer consists of a pair of serially connected inverters. The outputs of the first eight buffers (i.e., AND gate 112 and the first seven inverter-based buffers 114) in delay chain 110 are applied to the inputs of a first (8×1) multiplexer (mux) 120_1. Similarly, the outputs of the next eight inverter-based buffers 114 are applied to the inputs of a second (8×1) mux 120_2, and so on until the outputs of the last eight inverter-based buffers 114 are applied to the input of a sixteenth (8×1) mux 120_16. The outputs of the 16 muxes 120_1 to 120_16 are determined by the three bits SEL<2:0> of the 7-bit delay code SEL. For example, if SEL<2:0> is [000], then each mux 120—i outputs its first input signal. Similarly, if SEL<2:0> is [001], then each mux 120—i outputs its second input signal, and so on. Muxes 120_1 to 120_16 form a first stage of muxes in delay element 100.
The outputs of the first eight (8×1) muxes 120_1 to 120_8 are applied to the inputs of (8×1) mux 140_1, while the outputs of the last eight (8×1) muxes 120_9 to 120_16 are applied to the inputs of (8×1) mux 140_2. The outputs of muxes 140_1 and 140_2 are determined by the three bits SEL<5:3> of the 7-bit delay code SEL. For example, if SEL<5:3> is [000], then each mux 140—i outputs its first input signal. Similarly, if SEL<5:3> is [001], then each mux 140—i outputs its second input signal, and so on. Muxes 140_1 and 140_2 form a second stage of muxes in delay element 100.
The outputs of muxes 140_1 and 140_2 are applied to the inputs of (2×1) mux 160. The output of mux 160 is determined by the one bit SEL<6> of the 7-bit delay code SEL. If SEL<6> is [0], then mux 160 outputs its first input signal. Similarly, if SEL<6> is [1], then mux 160 outputs its second input signal. Mux 160 forms a third stage of muxes in delay element 100.
In this way, by setting delay code SEL<6:0> to the appropriate 7-bit value, delay element 100 will apply a desired one of the 128 different possible amounts of delay to input signal A in generating phase-shifted output signal Z.
As shown in FIG. 1, AND gate 112 receives both input signal A and an enable signal ENABLE that can be used to disable delay chain 110 and power down delay element 100. In particular, if the enable signal is high, then AND gate 112 allows input signal A to propagate through delay chain 110. As input signal A cycles between high and low, the 128 different buffers within delay chain 110 will also toggle between high and low, thereby consuming AC power. However, if the enable signal is low, then AND gate 112 blocks input signal A from propagating through delay chain 110. In that case, a continuous low signal will be applied to the rest of delay chain 110, and the 128 different buffers will not toggle, thereby reducing the consumption of AC power, effectively powering down delay element 100.
AND gate 112 can be used to reduce power consumption during operations of the receiver interface in which delay element 100 is not needed to apply a phase shift to input signal A. Note, however, that, when delay element 100 is used to apply a phase shift to input signal A, all 128 buffers in delay chain 110 will continue to toggle with every change in input signal A between high and low, no matter what amount of delay is selected for output signal Z. As a result and for example, the amount of power consumed by delay element 100 will be substantially the same if delay element 100 is controlled to select the output of the first buffer (i.e., AND gate 112) as output signal Z (i.e., by setting SEL<6:0> to [0000000]) or if delay element 100 is controlled to select the output of the last buffer (i.e., the 127th inverter-based buffer 114) as output signal Z (i.e., by setting SEL<6:0> to [1111111]).
Another problem with delay element 100 relates to glitches that can occur when the DLL-based controller (not shown in FIG. 1) changes the value of delay code SEL<6:0> to adjust the amount of delay applied by delay element 100. Such delay code updates can result in temporary transitions (i.e., glitches) in output signal Z that, in turn, can adversely affect downstream processing resulting in data corruption and/or word misalignment.